Triple
T9417700
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | IBM 3081 |
E227069
|
entity |
| Predicate | instanceOf |
P0
|
FINISHED |
| Object | IBM System/370-compatible processor |
C25416
|
CONCEPT FINISHED |
How this triple was built (1 step)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
CD
Concept disambiguation
gpt-5-mini-2025-08-07
Target class: IBM System/370-compatible processor Context triple: [IBM 3081, instanceOf, IBM System/370-compatible processor]
-
A.
mainframe computer series
A mainframe computer series is a family of high-performance, large-scale computers designed for reliable, centralized processing of massive workloads and critical enterprise applications over multiple generations.
-
B.
mainframe computer
chosen
A mainframe computer is a large, powerful, and highly reliable central computer system designed to process vast amounts of data and support numerous simultaneous users and critical applications, typically used by large organizations.
-
C.
Motorola 680x0 family processor
A Motorola 680x0 family processor is a 32-bit CISC microprocessor architecture used in many 1980s–1990s computers and workstations, known for its orthogonal instruction set and influential role in systems like the Apple Macintosh, Amiga, and Atari ST.
-
D.
8-bit computer family
A 8-bit computer family is a group of closely related computer models built around an 8-bit processor architecture, sharing a common instruction set, design philosophy, and often compatible hardware and software ecosystems.
-
E.
RISC server family
A RISC server family is a line of server systems built around Reduced Instruction Set Computing processors, optimized for high-performance, scalable, and efficient execution of server workloads.
- F. None of above.
Provenance (1 batch)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69ca84359e7c819091148ba4b670e436 |
completed | March 30, 2026, 2:09 p.m. |
Created at: March 30, 2026, 7:48 p.m.