Triple

T9027021
Position Surface form Disambiguated ID Type / Status
Subject Velocity Engine E216072 entity
Predicate basedOn P98 FINISHED
Object AltiVec technology E41460 NE FINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: AltiVec technology | Statement: [Velocity Engine, basedOn, AltiVec technology]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: AltiVec technology
Context triple: [Velocity Engine, basedOn, AltiVec technology]
  • A. AltiVec chosen
    AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
  • B. PowerPC
    PowerPC is a RISC-based microprocessor architecture developed in the early 1990s by the AIM alliance (Apple, IBM, and Motorola) and used in a wide range of computers, embedded systems, and game consoles.
  • C. PowerPC 74xx
    PowerPC 74xx is a family of 32-bit PowerPC G4 microprocessors used in many Apple Macintosh computers and embedded systems in the late 1990s and early 2000s.
  • D. 3DNow!
    3DNow! is a SIMD instruction set extension developed by AMD to accelerate floating-point and multimedia processing, particularly for 3D graphics and gaming workloads.
  • E. QorIQ communications processors
    QorIQ communications processors are a family of high-performance, power-efficient multicore system-on-chip devices designed for networking, telecommunications, and embedded communications applications.
  • F. None of above.
  • G. Unsure - the case is ambiguous/there is not enough information to decide.

Provenance (3 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69ca83a5fa88819088144801b4dd7245 completed March 30, 2026, 2:07 p.m.
NER Named-entity recognition batch_69cc6a7eb5b881908ace0c3327f06161 completed April 1, 2026, 12:44 a.m.
NED1 Entity disambiguation (via context triple) batch_69cfeb7a95a88190a41ba5549f2b2d5a completed April 3, 2026, 4:31 p.m.
Created at: March 30, 2026, 7:07 p.m.