Triple

T8472014
Position Surface form Disambiguated ID Type / Status
Subject Howard W. Johnson E200301 entity
Predicate notableWork P4 FINISHED
Object High-Speed Digital Design: A Handbook of Black Magic
High-Speed Digital Design: A Handbook of Black Magic is a widely respected engineering reference that explains the theory and practical techniques for designing reliable high-speed digital circuits and systems.
E736602 NE FINISHED

How this triple was built (4 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: High-Speed Digital Design: A Handbook of Black Magic | Statement: [Howard W. Johnson, notableWork, High-Speed Digital Design: A Handbook of Black Magic]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: High-Speed Digital Design: A Handbook of Black Magic
Context triple: [Howard W. Johnson, notableWork, High-Speed Digital Design: A Handbook of Black Magic]
  • A. Mead–Conway VLSI design revolution
    The Mead–Conway VLSI design revolution was a transformative shift in microchip design methodology that introduced simplified, scalable design rules and modular, high-level approaches, enabling widespread, university-level integrated circuit design and catalyzing the modern semiconductor industry.
  • B. VLSI theory
    VLSI theory is a field of computer science and electrical engineering that studies the design, analysis, and complexity of highly parallel and efficient digital circuits and systems built with very-large-scale integration technology.
  • C. Altera Hardware Description Language
    Altera Hardware Description Language (AHDL) is a proprietary hardware description language developed by Altera for designing and implementing digital logic circuits on its programmable logic devices.
  • D. IEEE Standard for High-Speed Test Access Port and Boundary-Scan Architecture
    IEEE 1149.10 is a JTAG-related IEEE standard that defines a high-speed test access and boundary-scan architecture for efficient testing and debugging of complex digital integrated circuits and systems.
  • E. FPGA
    An FPGA (Field-Programmable Gate Array) is a reconfigurable integrated circuit that can be programmed after manufacturing to implement custom digital logic functions and hardware designs.
  • F. None of above. chosen
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: High-Speed Digital Design: A Handbook of Black Magic
Triple: [Howard W. Johnson, notableWork, High-Speed Digital Design: A Handbook of Black Magic]
Generated description
High-Speed Digital Design: A Handbook of Black Magic is a widely respected engineering reference that explains the theory and practical techniques for designing reliable high-speed digital circuits and systems.
NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07
Target entity: High-Speed Digital Design: A Handbook of Black Magic
Target entity description: High-Speed Digital Design: A Handbook of Black Magic is a widely respected engineering reference that explains the theory and practical techniques for designing reliable high-speed digital circuits and systems.
  • A. Mead–Conway VLSI design revolution
    The Mead–Conway VLSI design revolution was a transformative shift in microchip design methodology that introduced simplified, scalable design rules and modular, high-level approaches, enabling widespread, university-level integrated circuit design and catalyzing the modern semiconductor industry.
  • B. VLSI theory
    VLSI theory is a field of computer science and electrical engineering that studies the design, analysis, and complexity of highly parallel and efficient digital circuits and systems built with very-large-scale integration technology.
  • C. Altera Hardware Description Language
    Altera Hardware Description Language (AHDL) is a proprietary hardware description language developed by Altera for designing and implementing digital logic circuits on its programmable logic devices.
  • D. IEEE Standard for High-Speed Test Access Port and Boundary-Scan Architecture
    IEEE 1149.10 is a JTAG-related IEEE standard that defines a high-speed test access and boundary-scan architecture for efficient testing and debugging of complex digital integrated circuits and systems.
  • E. FPGA
    An FPGA (Field-Programmable Gate Array) is a reconfigurable integrated circuit that can be programmed after manufacturing to implement custom digital logic functions and hardware designs.
  • F. None of above. chosen

Provenance (5 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69ca831a4f348190bfdd09250e86ae35 completed March 30, 2026, 2:05 p.m.
NER Named-entity recognition batch_69cbe4f3a81881908f20514579945ffa completed March 31, 2026, 3:14 p.m.
NED1 Entity disambiguation (via context triple) batch_69ce39fc9bf481908e37919b13465d18 completed April 2, 2026, 9:42 a.m.
NEDg Description generation batch_69ce3b1e188c8190ad894478141f6501 completed April 2, 2026, 9:47 a.m.
NED2 Entity disambiguation (via description) batch_69ce3bfd00948190b3956be3f8c5d547 completed April 2, 2026, 9:50 a.m.
Created at: March 30, 2026, 6:11 p.m.