Triple
T8436057
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | SBus |
E199225
|
entity |
| Predicate | instanceOf |
P0
|
FINISHED |
| Object | computer bus architecture |
C164
|
CONCEPT FINISHED |
How this triple was built (1 step)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
CD
Concept disambiguation
gpt-5-mini-2025-08-07
Target class: computer bus architecture Context triple: [SBus, instanceOf, computer bus architecture]
-
A.
computer architecture
Computer architecture is the conceptual design and organization of a computer system’s fundamental components and their interactions, defining how hardware and software work together to execute instructions efficiently.
-
B.
microprocessor architecture
Microprocessor architecture is the conceptual design and organization of a computer’s central processing unit, defining its instruction set, data paths, control logic, memory hierarchy, and interfaces to efficiently execute programs.
-
C.
VMEbus system
A VMEbus system is a modular computer architecture that uses a shared parallel bus to interconnect processors, memory, and I/O boards in a standardized backplane for industrial and embedded applications.
-
D.
computer hardware interface
chosen
A computer hardware interface is the physical and logical connection standard that enables communication and data exchange between a computer’s internal components or external devices and the system.
-
E.
historical computer architecture
Historical computer architecture is the study and classification of past computer system designs, components, and organizational principles that shaped the evolution of computing hardware over time.
- F. None of above.
Provenance (1 batch)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69ca8314cd6c8190a6b8c2a1096e18f3 |
completed | March 30, 2026, 2:05 p.m. |
Created at: March 30, 2026, 6:08 p.m.