Triple

T8284580
Position Surface form Disambiguated ID Type / Status
Subject Microprocessor without Interlocked Pipeline Stages E193757 entity
Predicate hasExtension P455 FINISHED
Object MIPS DSP extensions E37330 NE FINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: MIPS DSP extensions | Statement: [Microprocessor without Interlocked Pipeline Stages, hasExtension, MIPS DSP extensions]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07 
Target entity: MIPS DSP extensions
Context triple: [Microprocessor without Interlocked Pipeline Stages, hasExtension, MIPS DSP extensions]
  • A. MIPS chosen
    MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
  • B. RISC architecture
    RISC architecture is a CPU design philosophy that uses a small, highly optimized set of simple instructions to achieve high performance and efficiency.
  • C. SPARC microprocessor architecture
    The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
  • D. DSP-16
    DSP-16 was a U.S. Defense Support Program early-warning satellite used to detect missile launches and nuclear explosions from geostationary orbit.
  • E. Tensilica Xtensa LX6
    Tensilica Xtensa LX6 is a customizable 32-bit RISC processor core widely used in embedded systems for its efficient performance and low power consumption, notably in Espressif’s ESP32 SoCs.
  • F. None of above.
  • G. Unsure - the case is ambiguous/there is not enough information to decide.

Provenance (3 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69ca82e217a48190880695635c44b2ed completed March 30, 2026, 2:04 p.m.
NER Named-entity recognition batch_69cb7ad0535081908bb234cfc0e32b32 completed March 31, 2026, 7:42 a.m.
NED1 Entity disambiguation (via context triple) batch_69cd687e64a08190a45a1cf5f5c32291 completed April 1, 2026, 6:48 p.m.
Created at: March 30, 2026, 5:52 p.m.