Triple

T8284127
Position Surface form Disambiguated ID Type / Status
Subject V (vector extension) E193749 entity
Predicate compatibleWith P203 FINISHED
Object RISC-V floating-point extensions E37329 NE FINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: RISC-V floating-point extensions | Statement: [V (vector extension), compatibleWith, RISC-V floating-point extensions]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07 
Target entity: RISC-V floating-point extensions
Context triple: [V (vector extension), compatibleWith, RISC-V floating-point extensions]
  • A. RISC-V chosen
    RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
  • B. V (vector extension)
    V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
  • C. IEEE 754 floating‑point arithmetic standard
    The IEEE 754 floating‑point arithmetic standard is the globally adopted specification that defines formats and rules for representing and performing binary and decimal floating‑point calculations in computer systems.
  • D. Spike RISC-V ISA simulator
    Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
  • E. VFP floating-point extension
    The VFP floating-point extension is an ARM architecture coprocessor feature that provides hardware support for high-performance single- and double-precision floating-point arithmetic.
  • F. None of above.
  • G. Unsure - the case is ambiguous/there is not enough information to decide.

Provenance (3 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69ca82e217a48190880695635c44b2ed completed March 30, 2026, 2:04 p.m.
NER Named-entity recognition batch_69cb7ad0535081908bb234cfc0e32b32 completed March 31, 2026, 7:42 a.m.
NED1 Entity disambiguation (via context triple) batch_69cd687e64a08190a45a1cf5f5c32291 completed April 1, 2026, 6:48 p.m.
Created at: March 30, 2026, 5:52 p.m.