Triple
T8284045
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | RV128I |
E193747
|
entity |
| Predicate | specificationBody |
P62422
|
FINISHED |
| Object | RISC-V International (for future standardization) |
E192921
|
NE FINISHED |
How this triple was built (3 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: RISC-V International (for future standardization) | Statement: [RV128I, specificationBody, RISC-V International (for future standardization)]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: RISC-V International (for future standardization) Context triple: [RV128I, specificationBody, RISC-V International (for future standardization)]
-
A.
RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
-
B.
RISC-V International
chosen
RISC-V International is the global nonprofit consortium that oversees the development, standardization, and promotion of the open RISC-V instruction set architecture.
-
C.
Spike RISC-V ISA simulator
Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
-
D.
SiFive
SiFive is a semiconductor company known for designing customizable RISC‑V processor cores and platforms used in a wide range of computing applications.
-
E.
RISC architecture
RISC architecture is a CPU design philosophy that uses a small, highly optimized set of simple instructions to achieve high performance and efficiency.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
PD
Predicate disambiguation
gpt-5-mini-2025-08-07
Target predicate: specificationBody Context triple: [RV128I, specificationBody, RISC-V International (for future standardization)]
-
A.
primarySpecification
Indicates that one specification is the main or authoritative specification associated with an entity, distinguishing it from any secondary or supplementary specifications.
-
B.
definedBody
chosen
Indicates that one entity serves as the formal specification, content, or body definition of another entity.
-
C.
hasSpecification
Indicates that an entity is associated with a particular specification that defines or constrains its properties, behavior, or requirements.
-
D.
definesBody
Indicates that one entity specifies or determines the physical structure, form, or composition of another entity’s body.
-
E.
hasSpecificationSection
Indicates that an entity includes or is associated with a particular section dedicated to specifications.
- F. None of above.
Provenance (4 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69ca82e217a48190880695635c44b2ed |
completed | March 30, 2026, 2:04 p.m. |
| NER | Named-entity recognition | batch_69cb7ad0535081908bb234cfc0e32b32 |
completed | March 31, 2026, 7:42 a.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69cd687e64a08190a45a1cf5f5c32291 |
completed | April 1, 2026, 6:48 p.m. |
| PD | Predicate disambiguation | batch_69cb70ad9fc081908741f8c4a4141edf |
completed | March 31, 2026, 6:58 a.m. |
Created at: March 30, 2026, 5:52 p.m.