Triple
T8284043
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | RV128I |
E193747
|
entity |
| Predicate | relatedTo |
P37
|
FINISHED |
| Object | RV64I |
E37329
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: RV64I | Statement: [RV128I, relatedTo, RV64I]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: RV64I Context triple: [RV128I, relatedTo, RV64I]
-
A.
RISC-V
chosen
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
-
B.
AVX-512
AVX-512 is an advanced SIMD instruction set for x86 processors that enables high-throughput parallel processing using 512-bit wide vector operations.
-
C.
ARMv8-A
ARMv8-A is a 64-bit ARM processor architecture generation that introduces the AArch64 execution state and underpins many modern mobile and desktop CPUs.
-
D.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
E.
SiFive
SiFive is a semiconductor company known for designing customizable RISC‑V processor cores and platforms used in a wide range of computing applications.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69ca82e217a48190880695635c44b2ed |
completed | March 30, 2026, 2:04 p.m. |
| NER | Named-entity recognition | batch_69cb7ad0535081908bb234cfc0e32b32 |
completed | March 31, 2026, 7:42 a.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69cd687e64a08190a45a1cf5f5c32291 |
completed | April 1, 2026, 6:48 p.m. |
Created at: March 30, 2026, 5:52 p.m.