Triple
T712701
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | AMD processors |
E14244
|
entity |
| Predicate | alsoKnownAs |
P39
|
FINISHED |
| Object | AMD APUs |
E14244
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: AMD APUs | Statement: [AMD processors, alsoKnownAs, AMD APUs]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: AMD APUs Context triple: [AMD processors, alsoKnownAs, AMD APUs]
-
A.
AMD processors
chosen
AMD processors are a family of CPUs and APUs from Advanced Micro Devices known for offering strong multi-core performance and competitive pricing across desktops, laptops, and mobile devices.
-
B.
Intel Arc
Intel Arc is a line of discrete graphics processing units (GPUs) developed by Intel for gaming, content creation, and high-performance graphics workloads.
-
C.
Advanced Micro Devices
Advanced Micro Devices (AMD) is a major American semiconductor company best known for designing x86 processors and graphics chips that compete with Intel and NVIDIA in the global PC and data center markets.
-
D.
Intel Atom
Intel Atom is a line of low-power x86 microprocessors designed primarily for energy-efficient laptops, netbooks, and embedded devices.
-
E.
AMD64 architecture
The AMD64 architecture is a 64-bit instruction set architecture introduced by AMD that extends the x86 design to support larger memory addressing and enhanced performance while maintaining backward compatibility with 32-bit software.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69a4934a36e081909e7abef98b898a4e |
completed | March 1, 2026, 7:28 p.m. |
| NER | Named-entity recognition | batch_69a4a55dd5908190bfb8816f65ea02e1 |
completed | March 1, 2026, 8:45 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69a64a5851548190adeacb2feb35a1cb |
completed | March 3, 2026, 2:41 a.m. |
Created at: March 1, 2026, 7:36 p.m.