Triple

Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).

Phrase: SVE Scalable Vector Extension | Statement: [ARM, hasExtension, SVE Scalable Vector Extension]

Target entity: SVE Scalable Vector Extension
Context triple: [ARM, hasExtension, SVE Scalable Vector Extension]

• A. AltiVec
  AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
• B. RISC-V
  RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
• C. SPARC microprocessor architecture
  The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
• D. ARM
  ARM is a family of energy-efficient RISC processor architectures widely used in mobile devices, embedded systems, and increasingly in laptops and servers.
• E. MIPS
  MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
• F. None of above. chosen
• G. Unsure - the case is ambiguous/there is not enough information to decide.

Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"

Entity: SVE Scalable Vector Extension
Triple: [ARM, hasExtension, SVE Scalable Vector Extension]

SVE Scalable Vector Extension is an ARM architecture SIMD extension that enables scalable, vector-length-agnostic data parallel processing for high-performance and scientific computing workloads.

Target entity: SVE Scalable Vector Extension
Target entity description: SVE Scalable Vector Extension is an ARM architecture SIMD extension that enables scalable, vector-length-agnostic data parallel processing for high-performance and scientific computing workloads.

• A. AltiVec
  AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
• B. RISC-V
  RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
• C. SPARC microprocessor architecture
  The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
• D. ARM chosen
  ARM is a family of energy-efficient RISC processor architectures widely used in mobile devices, embedded systems, and increasingly in laptops and servers.
• E. MIPS
  MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
• F. None of above.