Triple

T5215668
Position Surface form Disambiguated ID Type / Status
Subject Indy workstation E117746 entity
Predicate cpuFamily P11217 FINISHED
Object MIPS R4000 series E37330 NE FINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: MIPS R4000 series | Statement: [Indy workstation, cpuFamily, MIPS R4000 series]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: MIPS R4000 series
Context triple: [Indy workstation, cpuFamily, MIPS R4000 series]
  • A. Risc PC
    Risc PC is a modular personal computer introduced by Acorn Computers in the 1990s, known for its RISC-based architecture and expandability.
  • B. Motorola 88000 family
    The Motorola 88000 family is a RISC-based microprocessor line developed by Motorola as a high-performance follow-up to its earlier 68000 series, aimed primarily at workstations and embedded systems.
  • C. Hitachi SH-4
    The Hitachi SH-4 is a 32-bit RISC microprocessor known for its use in late-1990s gaming consoles and embedded systems, featuring strong floating-point performance for 3D graphics.
  • D. Acorn RISC Machine
    Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
  • E. MIPS chosen
    MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
  • F. None of above.
  • G. Unsure - the case is ambiguous/there is not enough information to decide.

Provenance (3 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69bd4464ba3c8190bc16b2ebbe42ddb0 completed March 20, 2026, 12:58 p.m.
NER Named-entity recognition batch_69bd7a93fcc08190a1d2d025b4365d5a completed March 20, 2026, 4:49 p.m.
NED1 Entity disambiguation (via context triple) batch_69bf21a819f08190a67a92d8afa82e22 completed March 21, 2026, 10:54 p.m.
Created at: March 20, 2026, 1:48 p.m.