Triple
T5215667
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Indy workstation |
E117746
|
entity |
| Predicate | cpuArchitecture |
P8609
|
FINISHED |
| Object | MIPS |
E37330
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: MIPS | Statement: [Indy workstation, cpuArchitecture, MIPS]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: MIPS Context triple: [Indy workstation, cpuArchitecture, MIPS]
-
A.
MIPS
chosen
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
B.
SPIM
SPIM was the former ICAO airport code for Jorge Chávez International Airport in Lima, Peru, before it was changed to SPJC.
-
C.
MMIX
MMIX is a 64-bit RISC-style hypothetical computer architecture designed by Donald Knuth as the pedagogical machine for later volumes of *The Art of Computer Programming*.
-
D.
Risc PC
Risc PC is a modular personal computer introduced by Acorn Computers in the 1990s, known for its RISC-based architecture and expandability.
-
E.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69bd4464ba3c8190bc16b2ebbe42ddb0 |
completed | March 20, 2026, 12:58 p.m. |
| NER | Named-entity recognition | batch_69bd7a93fcc08190a1d2d025b4365d5a |
completed | March 20, 2026, 4:49 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69bf06b04cd881909e31b4e533dc4ae8 |
completed | March 21, 2026, 8:59 p.m. |
Created at: March 20, 2026, 1:48 p.m.