Triple
T5167294
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | O2 workstations |
E116589
|
entity |
| Predicate | cpuFamily |
P11217
|
FINISHED |
| Object | MIPS R5000 |
E37330
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: MIPS R5000 | Statement: [O2 workstations, cpuFamily, MIPS R5000]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: MIPS R5000 Context triple: [O2 workstations, cpuFamily, MIPS R5000]
-
A.
Risc PC
Risc PC is a modular personal computer introduced by Acorn Computers in the 1990s, known for its RISC-based architecture and expandability.
-
B.
Acorn RISC Machine
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
-
C.
MIPS
chosen
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
D.
Hitachi SH-4
The Hitachi SH-4 is a 32-bit RISC microprocessor known for its use in late-1990s gaming consoles and embedded systems, featuring strong floating-point performance for 3D graphics.
-
E.
Motorola 68851
The Motorola 68851 is an external paged memory management unit (MMU) designed to work with Motorola 68020 processors, providing advanced virtual memory and protection features.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69bd445ff97c81909a2615cc56235470 |
completed | March 20, 2026, 12:58 p.m. |
| NER | Named-entity recognition | batch_69bd792c5ea88190b6aa0e519c744155 |
completed | March 20, 2026, 4:43 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69beefadfd3c81909d21c1a08daeca7f |
completed | March 21, 2026, 7:21 p.m. |
Created at: March 20, 2026, 1:45 p.m.