Triple
T501510
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | IEEE 1149.7 |
E10411
|
entity |
| Predicate | fullName |
P16
|
FINISHED |
| Object | IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture |
E10411
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture | Statement: [IEEE 1149.7, fullName, IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture Context triple: [IEEE 1149.7, fullName, IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture]
-
A.
IEEE 1149.1 JTAG boundary‑scan standard
The IEEE 1149.1 JTAG boundary-scan standard is a widely used test and debug specification that defines a serial interface and architecture for accessing and testing the internal logic and interconnects of integrated circuits and circuit boards.
-
B.
IEEE 1149 family of standards
The IEEE 1149 family of standards is a set of Joint Test Action Group (JTAG) boundary-scan specifications that define methods for testing, debugging, and accessing digital integrated circuits and boards.
-
C.
IEEE 1149.10
IEEE 1149.10 is a JTAG-related IEEE standard that defines high-speed test access mechanisms for embedded instrumentation and system-level testing of complex digital devices and boards.
-
D.
IEEE 1149.7
chosen
IEEE 1149.7 is a compact, enhanced version of the JTAG test and debug standard that reduces pin count and power while adding advanced debug and trace capabilities for modern integrated circuits.
-
E.
IEEE 1149.4
IEEE 1149.4 is a mixed-signal test bus standard that extends JTAG boundary-scan techniques to support testing and diagnosis of analog and mixed-signal circuits on printed circuit boards.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69a2e848adf881908e5e04f7af030093 |
completed | Feb. 28, 2026, 1:06 p.m. |
| NER | Named-entity recognition | batch_69a2f131e2148190afd43402f505c73e |
completed | Feb. 28, 2026, 1:44 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69a485456cfc81908fab6c5d9548ebb9 |
completed | March 1, 2026, 6:28 p.m. |
Created at: Feb. 28, 2026, 1:12 p.m.