Triple
T4942899
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | IECQ |
E110979
|
entity |
| Predicate | fullName |
P16
|
FINISHED |
| Object | IEC Quality Assessment System for Electronic Components |
E110979
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: IEC Quality Assessment System for Electronic Components | Statement: [IECQ, fullName, IEC Quality Assessment System for Electronic Components]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: IEC Quality Assessment System for Electronic Components Context triple: [IECQ, fullName, IEC Quality Assessment System for Electronic Components]
-
A.
IECQ
chosen
IECQ is the IEC Quality Assessment System for Electronic Components, a global certification scheme that ensures the quality and reliability of electronic components and related materials.
-
B.
IEEE 1500 embedded core test standard
The IEEE 1500 embedded core test standard defines a structured test access and wrapper architecture for testing individual IP cores within system-on-chip (SoC) designs.
-
C.
IEEE 1149 family of standards
The IEEE 1149 family of standards is a set of Joint Test Action Group (JTAG) boundary-scan specifications that define methods for testing, debugging, and accessing digital integrated circuits and boards.
-
D.
IEEE Std 610.12-2010
IEEE Std 610.12-2010 is an updated IEEE standard that provides a formal glossary of terms and definitions used in software engineering.
-
E.
IEEE Standard for High-Speed Test Access Port and Boundary-Scan Architecture
IEEE 1149.10 is a JTAG-related IEEE standard that defines a high-speed test access and boundary-scan architecture for efficient testing and debugging of complex digital integrated circuits and systems.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69bd441721cc819085c7e33fe0876818 |
completed | March 20, 2026, 12:56 p.m. |
| NER | Named-entity recognition | batch_69bd70a5f56481908365d0fe16892bf4 |
completed | March 20, 2026, 4:07 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69be77c421288190bcc2d9bfdfff7198 |
completed | March 21, 2026, 10:49 a.m. |
Created at: March 20, 2026, 1:31 p.m.