Triple

T415913
Position Surface form Disambiguated ID Type / Status
Subject IEEE 1149.6 E9591 entity
Predicate relatedTo P37 FINISHED
Object IEEE 1149.4
IEEE 1149.4 is a mixed-signal test bus standard that extends JTAG boundary-scan techniques to support testing and diagnosis of analog and mixed-signal circuits on printed circuit boards.
E55111 NE FINISHED

How this triple was built (4 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: IEEE 1149.4 | Statement: [IEEE 1149.6, relatedTo, IEEE 1149.4]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: IEEE 1149.4
Context triple: [IEEE 1149.6, relatedTo, IEEE 1149.4]
  • A. IEEE 1149.7
    IEEE 1149.7 is a compact, enhanced version of the JTAG test and debug standard that reduces pin count and power while adding advanced debug and trace capabilities for modern integrated circuits.
  • B. IEEE 1149.6
    IEEE 1149.6 is a boundary-scan test standard that extends JTAG to support structural testing of high-speed AC-coupled and differential digital interconnects on printed circuit boards.
  • C. IEEE 1149 family of standards
    The IEEE 1149 family of standards is a set of Joint Test Action Group (JTAG) boundary-scan specifications that define methods for testing, debugging, and accessing digital integrated circuits and boards.
  • D. IEEE 1149.1 JTAG boundary‑scan standard
    The IEEE 1149.1 JTAG boundary-scan standard is a widely used test and debug specification that defines a serial interface and architecture for accessing and testing the internal logic and interconnects of integrated circuits and circuit boards.
  • E. IEEE 1532
    IEEE 1532 is an extension of the JTAG boundary-scan standard that defines in-system programming and configuration procedures for programmable devices such as FPGAs and CPLDs.
  • F. None of above. chosen
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: IEEE 1149.4
Triple: [IEEE 1149.6, relatedTo, IEEE 1149.4]
Generated description
IEEE 1149.4 is a mixed-signal test bus standard that extends JTAG boundary-scan techniques to support testing and diagnosis of analog and mixed-signal circuits on printed circuit boards.
NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07
Target entity: IEEE 1149.4
Target entity description: IEEE 1149.4 is a mixed-signal test bus standard that extends JTAG boundary-scan techniques to support testing and diagnosis of analog and mixed-signal circuits on printed circuit boards.
  • A. IEEE 1149.7
    IEEE 1149.7 is a compact, enhanced version of the JTAG test and debug standard that reduces pin count and power while adding advanced debug and trace capabilities for modern integrated circuits.
  • B. IEEE 1149.6
    IEEE 1149.6 is a boundary-scan test standard that extends JTAG to support structural testing of high-speed AC-coupled and differential digital interconnects on printed circuit boards.
  • C. IEEE 1149 family of standards
    The IEEE 1149 family of standards is a set of Joint Test Action Group (JTAG) boundary-scan specifications that define methods for testing, debugging, and accessing digital integrated circuits and boards.
  • D. IEEE 1149.1 JTAG boundary‑scan standard
    The IEEE 1149.1 JTAG boundary-scan standard is a widely used test and debug specification that defines a serial interface and architecture for accessing and testing the internal logic and interconnects of integrated circuits and circuit boards.
  • E. IEEE 1532
    IEEE 1532 is an extension of the JTAG boundary-scan standard that defines in-system programming and configuration procedures for programmable devices such as FPGAs and CPLDs.
  • F. None of above. chosen

Provenance (5 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69a2e80111fc8190961d5b7c6154123f completed Feb. 28, 2026, 1:05 p.m.
NER Named-entity recognition batch_69a2ee8d835881908403ea23901e52b3 completed Feb. 28, 2026, 1:33 p.m.
NED1 Entity disambiguation (via context triple) batch_69a43667f180819099661c2cc5d8b188 completed March 1, 2026, 12:51 p.m.
NEDg Description generation batch_69a436e9fc9081909faf007c593e9537 completed March 1, 2026, 12:54 p.m.
NED2 Entity disambiguation (via description) batch_69a43755152881909a4dfa8b31a0aad6 completed March 1, 2026, 12:55 p.m.
Created at: Feb. 28, 2026, 1:09 p.m.