Triple

T415870
Position Surface form Disambiguated ID Type / Status
Subject IEEE 1149.6 E9591 entity
Predicate fullName P16 FINISHED
Object IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks E9591 NE FINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks | Statement: [IEEE 1149.6, fullName, IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks
Context triple: [IEEE 1149.6, fullName, IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks]
  • A. IEEE 1149.1 JTAG boundary‑scan standard
    The IEEE 1149.1 JTAG boundary-scan standard is a widely used test and debug specification that defines a serial interface and architecture for accessing and testing the internal logic and interconnects of integrated circuits and circuit boards.
  • B. IEEE 1149.6 chosen
    IEEE 1149.6 is a boundary-scan test standard that extends JTAG to support structural testing of high-speed AC-coupled and differential digital interconnects on printed circuit boards.
  • C. IEEE 1149.7
    IEEE 1149.7 is a compact, enhanced version of the JTAG test and debug standard that reduces pin count and power while adding advanced debug and trace capabilities for modern integrated circuits.
  • D. IEEE 1532
    IEEE 1532 is an extension of the JTAG boundary-scan standard that defines in-system programming and configuration procedures for programmable devices such as FPGAs and CPLDs.
  • E. IEEE Std 610.12-2010
    IEEE Std 610.12-2010 is an updated IEEE standard that provides a formal glossary of terms and definitions used in software engineering.
  • F. None of above.
  • G. Unsure - the case is ambiguous/there is not enough information to decide.

Provenance (3 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69a2e80111fc8190961d5b7c6154123f completed Feb. 28, 2026, 1:05 p.m.
NER Named-entity recognition batch_69a2ee8d835881908403ea23901e52b3 completed Feb. 28, 2026, 1:33 p.m.
NED1 Entity disambiguation (via context triple) batch_69a423a2ddb08190bdee170f843c2a19 completed March 1, 2026, 11:31 a.m.
Created at: Feb. 28, 2026, 1:09 p.m.