Triple
T3426704
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Acorn RISC Machine |
E72244
|
entity |
| Predicate | laterName |
P65
|
FINISHED |
| Object | Advanced RISC Machines |
E72244
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Advanced RISC Machines | Statement: [Acorn RISC Machine, laterName, Advanced RISC Machines]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: Advanced RISC Machines Context triple: [Acorn RISC Machine, laterName, Advanced RISC Machines]
-
A.
Acorn RISC Machine
chosen
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
-
B.
RISC architecture
RISC architecture is a CPU design philosophy that uses a small, highly optimized set of simple instructions to achieve high performance and efficiency.
-
C.
RISC II
RISC II is an early experimental reduced instruction set computer (RISC) processor developed at UC Berkeley that significantly shaped the design of later RISC architectures.
-
D.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
-
E.
Crusoe microprocessor
The Crusoe microprocessor is a low-power, x86-compatible CPU line from Transmeta that used code-morphing software to translate x86 instructions to an underlying VLIW architecture, targeting laptops and mobile devices.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69ad85ae14308190bcbc25cfa0246c0b |
completed | March 8, 2026, 2:20 p.m. |
| NER | Named-entity recognition | batch_69adb982792c8190b1163eee4252210f |
completed | March 8, 2026, 6:01 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69b35478448481908e1c0f717d99f992 |
completed | March 13, 2026, 12:04 a.m. |
Created at: March 8, 2026, 3:15 p.m.