Triple
T3421681
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Acorn Computers |
E72127
|
entity |
| Predicate | developed |
P73
|
FINISHED |
| Object | Acorn RISC Machine |
E72244
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Acorn RISC Machine | Statement: [Acorn Computers, developed, Acorn RISC Machine]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: Acorn RISC Machine Context triple: [Acorn Computers, developed, Acorn RISC Machine]
-
A.
Acorn RISC Machine
chosen
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
-
B.
Crusoe microprocessor
The Crusoe microprocessor is a low-power, x86-compatible CPU line from Transmeta that used code-morphing software to translate x86 instructions to an underlying VLIW architecture, targeting laptops and mobile devices.
-
C.
RISC II
RISC II is an early experimental reduced instruction set computer (RISC) processor developed at UC Berkeley that significantly shaped the design of later RISC architectures.
-
D.
Motorola 68851
The Motorola 68851 is an external paged memory management unit (MMU) designed to work with Motorola 68020 processors, providing advanced virtual memory and protection features.
-
E.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69ad85ad38e48190b7660c5118a35289 |
completed | March 8, 2026, 2:20 p.m. |
| NER | Named-entity recognition | batch_69adb950f65481908c4aad15516e7a7c |
completed | March 8, 2026, 6 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69b35472881c8190baf90b91daa924ec |
completed | March 13, 2026, 12:04 a.m. |
Created at: March 8, 2026, 3:15 p.m.