Triple
T3421680
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Acorn Computers |
E72127
|
entity |
| Predicate | developed |
P73
|
FINISHED |
| Object | ARM architecture |
E13771
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: ARM architecture | Statement: [Acorn Computers, developed, ARM architecture]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: ARM architecture Context triple: [Acorn Computers, developed, ARM architecture]
-
A.
ARM
chosen
ARM is a family of energy-efficient RISC processor architectures widely used in mobile devices, embedded systems, and increasingly in laptops and servers.
-
B.
ARMv7-A architecture
ARMv7-A architecture is a 32-bit ARM processor architecture widely used in smartphones, tablets, and embedded systems, featuring advanced performance, virtualization, and security capabilities.
-
C.
ARMv6 architecture family
The ARMv6 architecture family is a generation of 32-bit ARM processor designs that introduced significant enhancements in performance, multimedia processing, and security features for mobile and embedded devices.
-
D.
ARMv8-A
ARMv8-A is a 64-bit ARM processor architecture generation that introduces the AArch64 execution state and underpins many modern mobile and desktop CPUs.
-
E.
ARMv5 architecture
ARMv5 architecture is a 32-bit RISC processor architecture from ARM that introduced enhancements over earlier ARM generations, including support for more advanced instruction sets and extensions used in many embedded and mobile devices.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69ad85ad38e48190b7660c5118a35289 |
completed | March 8, 2026, 2:20 p.m. |
| NER | Named-entity recognition | batch_69adb950f65481908c4aad15516e7a7c |
completed | March 8, 2026, 6 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69b373a2271081908816fbf6cac06975 |
completed | March 13, 2026, 2:17 a.m. |
Created at: March 8, 2026, 3:15 p.m.