Triple
T30204841
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Hitachi 6301 |
E767884
|
entity |
| Predicate | instanceOf |
P0
|
FINISHED |
| Object | 8-bit microcontroller |
C24738
|
CONCEPT FINISHED |
How this triple was built (1 step)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
CD
Concept disambiguation
gpt-5-mini-2025-08-07
Target class: 8-bit microcontroller Context triple: [Hitachi 6301, instanceOf, 8-bit microcontroller]
-
A.
8-bit microprocessor
An 8-bit microprocessor is a central processing unit that processes data and instructions in 8-bit chunks, typically featuring an 8-bit data bus and registers, and used in simple computing and embedded systems.
-
B.
microcontroller
chosen
A microcontroller is a compact integrated circuit designed to execute programmed instructions and control electronic systems by combining a processor, memory, and input/output peripherals on a single chip.
-
C.
single-board microcontroller
A single-board microcontroller is a compact, self-contained circuit board that integrates a microcontroller chip with essential components like power regulation, input/output interfaces, and programming connections for embedded control applications.
-
D.
CMOS microprocessor
A CMOS microprocessor is a central processing unit implemented using complementary metal-oxide-semiconductor technology, providing high integration, low power consumption, and reliable digital computation on a single chip.
-
E.
4-bit RAM chip
A 4-bit RAM chip is a small memory device that can store and retrieve 4-bit-wide data words at specific address locations under control of read/write signals.
- F. None of above.
Provenance (1 batch)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69f2247eb0848190b4032f302d39c0d9 |
completed | April 29, 2026, 3:32 p.m. |
Created at: April 29, 2026, 7:31 p.m.