Triple
T26733593
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Intel 4004 |
E674040
|
entity |
| Predicate | instanceOf |
P0
|
FINISHED |
| Object | first commercial microprocessor |
C4925
|
CONCEPT FINISHED |
How this triple was built (1 step)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
CD
Concept disambiguation
gpt-5-mini-2025-08-07
Target class: first commercial microprocessor Context triple: [Intel 4004, instanceOf, first commercial microprocessor]
-
A.
CMOS microprocessor
A CMOS microprocessor is a central processing unit implemented using complementary metal-oxide-semiconductor technology, providing high integration, low power consumption, and reliable digital computation on a single chip.
-
B.
8-bit microprocessor
An 8-bit microprocessor is a central processing unit that processes data and instructions in 8-bit chunks, typically featuring an 8-bit data bus and registers, and used in simple computing and embedded systems.
-
C.
PDP series computer
A PDP series computer is a family of minicomputers produced by Digital Equipment Corporation (DEC) from the 1960s to 1980s, known for their relatively low cost, interactive use, and significant influence on computer architecture and operating systems.
-
D.
S-100 bus computer
An S-100 bus computer is a microcomputer system built around the S-100 expansion bus standard, using a backplane and plug-in cards for CPU, memory, and I/O to create a modular, expandable architecture.
-
E.
microprocessor
chosen
A microprocessor is a compact, integrated circuit that performs the arithmetic, logic, control, and input/output operations of a computer’s central processing unit (CPU) on a single chip.
- F. None of above.
Provenance (1 batch)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69eecda57ab481909424e98f2835e7d8 |
completed | April 27, 2026, 2:44 a.m. |
Created at: April 27, 2026, 3:46 a.m.