Triple
T25550503
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | VIA Technologies |
E640425
|
entity |
| Predicate | product |
P490
|
FINISHED |
| Object |
VIA KT series chipsets
The VIA KT series chipsets are a family of core logic chipsets designed by VIA Technologies to support AMD Athlon and Duron processors on desktop motherboards.
|
E1682627
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: VIA KT series chipsets | Statement: [VIA Technologies, product, VIA KT series chipsets]
NEDg
Description generation
gpt-5.1
Instruction
Generate a one-sentence description of the target entity. You are given a context triple in the form (subject, predicate, object), where the object is the target entity. # Instructions Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. Avoid repeating the information from the triple, unless really essential. # Response Format Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: VIA KT series chipsets Triple: [VIA Technologies, product, VIA KT series chipsets]
Generated description
The VIA KT series chipsets are a family of core logic chipsets designed by VIA Technologies to support AMD Athlon and Duron processors on desktop motherboards.
Provenance (5 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69e75dc101a881909fd33b02174e9768 |
completed | April 21, 2026, 11:21 a.m. |
| NER | Named-entity recognition | batch_69f5f8c583e48190a2a1f65d80a2b589 |
completed | May 2, 2026, 1:14 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_6a10ad9ec2e881909c295f5b3a3f16c5 |
completed | May 22, 2026, 7:25 p.m. |
| NEDg | Description generation | batch_6a10ae9972908190ac6b8a2a0d6eb144 |
completed | May 22, 2026, 7:29 p.m. |
| NED2 | Entity disambiguation (via description) | batch_6a10af45b9048190b1613ef21fa00caf |
completed | May 22, 2026, 7:32 p.m. |
Created at: April 21, 2026, 3:36 p.m.