Triple

Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).

Phrase: IEEE 1149.1 boundary-scan architecture | Statement: [IEEE 1149.10, complements, IEEE 1149.1 boundary-scan architecture]

Target entity: IEEE 1149.1 boundary-scan architecture
Context triple: [IEEE 1149.10, complements, IEEE 1149.1 boundary-scan architecture]

• A. IEEE 1149.1 JTAG boundary‑scan standard chosen
  The IEEE 1149.1 JTAG boundary-scan standard is a widely used test and debug specification that defines a serial interface and architecture for accessing and testing the internal logic and interconnects of integrated circuits and circuit boards.
• B. IEEE Standard for High-Speed Test Access Port and Boundary-Scan Architecture
  IEEE 1149.10 is a JTAG-related IEEE standard that defines a high-speed test access and boundary-scan architecture for efficient testing and debugging of complex digital integrated circuits and systems.
• C. IEEE 1149 family of standards
  The IEEE 1149 family of standards is a set of Joint Test Action Group (JTAG) boundary-scan specifications that define methods for testing, debugging, and accessing digital integrated circuits and boards.
• D. IEEE 1149.4
  IEEE 1149.4 is a mixed-signal test bus standard that extends JTAG boundary-scan techniques to support testing and diagnosis of analog and mixed-signal circuits on printed circuit boards.
• E. IEEE 1149.10
  IEEE 1149.10 is a JTAG-related IEEE standard that defines high-speed test access mechanisms for embedded instrumentation and system-level testing of complex digital devices and boards.
• F. None of above.
• G. Unsure - the case is ambiguous/there is not enough information to decide.