Triple
T20399544
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | SGI Indy |
E500294
|
entity |
| Predicate | cpu |
P8608
|
FINISHED |
| Object | MIPS R4600 |
—
|
NE NERFINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: MIPS R4600 | Statement: [SGI Indy, cpu, MIPS R4600]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: MIPS R4600 Context triple: [SGI Indy, cpu, MIPS R4600]
-
A.
MIPS R4600
chosen
The MIPS R4600 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
B.
MIPS R5000
The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
C.
MIPS R2000
The MIPS R2000 is an early 32-bit RISC microprocessor that helped popularize the MIPS architecture in academic and commercial systems during the late 1980s.
-
D.
R4000
The R4000 is a 64-bit MIPS microprocessor that introduced a new generation of high-performance, RISC-based CPU designs widely used in workstations and servers in the early 1990s.
-
E.
MIPS II
MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (2 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69e0b4a81bec8190b69adfdc1336a015 |
completed | April 16, 2026, 10:06 a.m. |
| NER | Named-entity recognition | batch_69e6798cf04481909f183c4c75fe6d52 |
completed | April 20, 2026, 7:07 p.m. |
Created at: April 16, 2026, 11:29 a.m.