Triple
T20399538
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | SGI Indy |
E500294
|
entity |
| Predicate | instanceOf |
P0
|
FINISHED |
| Object | RISC workstation |
C9935
|
CONCEPT FINISHED |
How this triple was built (1 step)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
CD
Concept disambiguation
gpt-5-mini-2025-08-07
Target class: RISC workstation Context triple: [SGI Indy, instanceOf, RISC workstation]
-
A.
RISC workstation family
chosen
A RISC workstation family is a series of high-performance desktop or server computers built around Reduced Instruction Set Computing processors, designed for technical, scientific, or engineering applications requiring efficient computation and advanced graphics.
-
B.
Sun-3 series computer
The Sun-3 series computer is a family of 32-bit workstation and server systems produced by Sun Microsystems in the mid-1980s, based on Motorola 68020/68030 processors and designed to run the SunOS Unix operating system.
-
C.
Amiga computer
An Amiga computer is a family of personal computers developed by Commodore in the 1980s and early 1990s, known for their advanced multimedia capabilities, custom chipset, and multitasking operating system.
-
D.
RISC server family
A RISC server family is a line of server systems built around Reduced Instruction Set Computing processors, optimized for high-performance, scalable, and efficient execution of server workloads.
-
E.
Motorola 88000 family microprocessor
The Motorola 88000 family microprocessor is a series of 32-bit RISC CPUs developed by Motorola in the late 1980s, designed for high-performance computing and embedded systems with a clean, load-store architecture.
- F. None of above.
Provenance (1 batch)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69e0b4a81bec8190b69adfdc1336a015 |
completed | April 16, 2026, 10:06 a.m. |
Created at: April 16, 2026, 11:29 a.m.