Triple

T18704573
Position Surface form Disambiguated ID Type / Status
Subject SiFive E457337 entity
Predicate notableProductFamily P11218 FINISHED
Object SiFive Performance
SiFive Performance is a family of high-performance RISC‑V processor cores designed by SiFive for demanding computing applications.
E457337 NE FINISHED

How this triple was built (4 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: SiFive Performance | Statement: [SiFive, notableProductFamily, SiFive Performance]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: SiFive Performance
Context triple: [SiFive, notableProductFamily, SiFive Performance]
  • A. SiFive
    SiFive is a semiconductor company known for designing customizable RISC‑V processor cores and platforms used in a wide range of computing applications.
  • B. RISC-V
    RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
  • C. Spike RISC-V ISA simulator
    Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
  • D. Tensilica
    Tensilica is a semiconductor IP company best known for its configurable Xtensa processor cores used in embedded and SoC designs.
  • E. sifive_u board
    The sifive_u board is a RISC-V development platform modeled in QEMU, commonly used for running and testing 64-bit RISC-V software in a virtualized environment.
  • F. None of above. chosen
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: SiFive Performance
Triple: [SiFive, notableProductFamily, SiFive Performance]
Generated description
SiFive Performance is a family of high-performance RISC‑V processor cores designed by SiFive for demanding computing applications.
NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07
Target entity: SiFive Performance
Target entity description: SiFive Performance is a family of high-performance RISC‑V processor cores designed by SiFive for demanding computing applications.
  • A. SiFive chosen
    SiFive is a semiconductor company known for designing customizable RISC‑V processor cores and platforms used in a wide range of computing applications.
  • B. RISC-V
    RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
  • C. Spike RISC-V ISA simulator
    Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
  • D. Tensilica
    Tensilica is a semiconductor IP company best known for its configurable Xtensa processor cores used in embedded and SoC designs.
  • E. sifive_u board
    The sifive_u board is a RISC-V development platform modeled in QEMU, commonly used for running and testing 64-bit RISC-V software in a virtualized environment.
  • F. None of above.

Provenance (5 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69d8d392aad081909fe31aa03e6e97d1 completed April 10, 2026, 10:40 a.m.
NER Named-entity recognition batch_69e5671665bc8190b9b4a4ce4ec5b2eb completed April 19, 2026, 11:36 p.m.
NED1 Entity disambiguation (via context triple) batch_6a053d282c28819082d95ac86ea7bdc3 completed May 14, 2026, 3:10 a.m.
NEDg Description generation batch_6a053dd2222c819095099ba116b1c0a7 completed May 14, 2026, 3:13 a.m.
NED2 Entity disambiguation (via description) batch_6a053e4b79d081908bddd0608ec1b519 completed May 14, 2026, 3:15 a.m.
Created at: April 10, 2026, 11:49 a.m.