Triple
T16783383
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | ARM Mali-G710 MP7 |
E407908
|
entity |
| Predicate | shaderCoreArchitecture |
P11219
|
FINISHED |
| Object | Valhall-based shader cores |
—
|
LITERAL FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Valhall-based shader cores | Statement: [ARM Mali-G710 MP7, shaderCoreArchitecture, Valhall-based shader cores]
PD
Predicate disambiguation
gpt-5-mini-2025-08-07
Target predicate: shaderCoreArchitecture Context triple: [ARM Mali-G710 MP7, shaderCoreArchitecture, Valhall-based shader cores]
-
A.
shaderUnits
Indicates the relationship between a graphics processor and the number or configuration of its shader processing units used for rendering and computation.
-
B.
graphicsArchitecture
chosen
Indicates the underlying design or structural framework that defines how a system’s graphics or visual rendering components are organized and operate.
-
C.
microarchitectureClass
Indicates that one entity is classified as a specific type or category of microarchitecture relative to another entity.
-
D.
cpuCoreMicroarchitecture
Indicates the specific microarchitecture design implemented in a given CPU core.
-
E.
microarchitectureFeature
Indicates a relationship where a specific microarchitecture possesses or supports a particular hardware or design feature.
- F. None of above.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69d8839270588190886720d9519bbf8f |
completed | April 10, 2026, 4:58 a.m. |
| NER | Named-entity recognition | batch_69e3b218d31881908d896e688ebd171c |
completed | April 18, 2026, 4:32 p.m. |
| PD | Predicate disambiguation | batch_69e319cf691c819083e39225f5777ef0 |
completed | April 18, 2026, 5:42 a.m. |
Created at: April 10, 2026, 5:22 a.m.