Triple

T1634112
Position Surface form Disambiguated ID Type / Status
Subject John L. Hennessy E35324 entity
Predicate coFounded P104 FINISHED
Object MIPS Computer Systems E37330 NE FINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: MIPS Computer Systems | Statement: [John L. Hennessy, coFounded, MIPS Computer Systems]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07 
Target entity: MIPS Computer Systems
Context triple: [John L. Hennessy, coFounded, MIPS Computer Systems]
  • A. MIPS chosen
    MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
  • B. Acorn RISC Machine
    Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
  • C. Motorola 88000 family
    The Motorola 88000 family is a RISC-based microprocessor line developed by Motorola as a high-performance follow-up to its earlier 68000 series, aimed primarily at workstations and embedded systems.
  • D. Motorola 68000 family
    The Motorola 68000 family is a line of 16/32-bit CISC microprocessors widely used in early personal computers, workstations, and game consoles during the 1980s and early 1990s.
  • E. SPARC microprocessor architecture
    The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
  • F. None of above.
  • G. Unsure - the case is ambiguous/there is not enough information to decide.

Provenance (3 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69a886036bc081909ff5de16dbe5e8ea completed March 4, 2026, 7:20 p.m.
NER Named-entity recognition batch_69a909f86abc8190b0b81310dcd7feed completed March 5, 2026, 4:43 a.m.
NED1 Entity disambiguation (via context triple) batch_69ad6099979481908e2c506323d546dd completed March 8, 2026, 11:42 a.m.
Created at: March 4, 2026, 7:28 p.m.