Triple

T15838887
Position Surface form Disambiguated ID Type / Status
Subject Einstein Observatory E384050 entity
Predicate scientificInstrument P13781 FINISHED
Object Imaging Proportional Counter (IPC)
The Imaging Proportional Counter (IPC) was an X-ray detector aboard the Einstein Observatory that provided spatially resolved measurements of cosmic X-ray sources.
 E1179648 NE FINISHED

How this triple was built (4 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Imaging Proportional Counter (IPC) | Statement: [Einstein Observatory, scientificInstrument, Imaging Proportional Counter (IPC)]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07 
Target entity: Imaging Proportional Counter (IPC)
Context triple: [Einstein Observatory, scientificInstrument, Imaging Proportional Counter (IPC)]
  • A. Independent Computing Architecture
    Independent Computing Architecture (ICA) is Citrix's proprietary protocol for delivering virtual applications and desktops over a network, enabling remote access to centralized computing resources.
  • B. SPARC microprocessor architecture
    The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
  • C. Xe-HPG microarchitecture
    Xe-HPG microarchitecture is Intel’s high-performance gaming-oriented GPU architecture designed to power its discrete Arc graphics cards with advanced features like hardware-accelerated ray tracing.
  • D. Intelligence Processing Unit
    The Intelligence Processing Unit is a specialized processor architecture designed by Graphcore to accelerate artificial intelligence and machine learning workloads with highly parallel, memory-rich compute.
  • E. Industrial Power Control (IPC)
    Industrial Power Control (IPC) is an Infineon Technologies division specializing in power semiconductor solutions for industrial applications such as drives, renewable energy, and power transmission.
  • F. None of above. chosen
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: Imaging Proportional Counter (IPC)
Triple: [Einstein Observatory, scientificInstrument, Imaging Proportional Counter (IPC)]
Generated description
The Imaging Proportional Counter (IPC) was an X-ray detector aboard the Einstein Observatory that provided spatially resolved measurements of cosmic X-ray sources.
NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07 
Target entity: Imaging Proportional Counter (IPC)
Target entity description: The Imaging Proportional Counter (IPC) was an X-ray detector aboard the Einstein Observatory that provided spatially resolved measurements of cosmic X-ray sources.
  • A. Independent Computing Architecture
    Independent Computing Architecture (ICA) is Citrix's proprietary protocol for delivering virtual applications and desktops over a network, enabling remote access to centralized computing resources.
  • B. SPARC microprocessor architecture
    The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
  • C. Xe-HPG microarchitecture
    Xe-HPG microarchitecture is Intel’s high-performance gaming-oriented GPU architecture designed to power its discrete Arc graphics cards with advanced features like hardware-accelerated ray tracing.
  • D. Intelligence Processing Unit
    The Intelligence Processing Unit is a specialized processor architecture designed by Graphcore to accelerate artificial intelligence and machine learning workloads with highly parallel, memory-rich compute.
  • E. Industrial Power Control (IPC)
    Industrial Power Control (IPC) is an Infineon Technologies division specializing in power semiconductor solutions for industrial applications such as drives, renewable energy, and power transmission.
  • F. None of above. chosen

Provenance (5 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69d86da34c888190976e06c4019d415a completed April 10, 2026, 3:25 a.m.
NER Named-entity recognition batch_69e142e4fa24819086a1a226082ac2d3 completed April 16, 2026, 8:13 p.m.
NED1 Entity disambiguation (via context triple) batch_69ffa13c931481908ed9fd10fddd867c completed May 9, 2026, 9:03 p.m.
NEDg Description generation batch_69ffa419c6dc81908c9678f8434530f8 completed May 9, 2026, 9:16 p.m.
NED2 Entity disambiguation (via description) batch_69ffa4cff5088190a7f11fd62941f4fb completed May 9, 2026, 9:19 p.m.
Created at: April 10, 2026, 4:49 a.m.