Triple
T1499593
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Intel 4004 |
E29765
|
entity |
| Predicate | instructionSetSize |
P28524
|
FINISHED |
| Object | 46 instructions |
—
|
LITERAL FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: 46 instructions | Statement: [Intel 4004, instructionSetSize, 46 instructions]
PD
Predicate disambiguation
gpt-5-mini-2025-08-07
Target predicate: instructionSetSize Context triple: [Intel 4004, instructionSetSize, 46 instructions]
-
A.
instructionSetType
Indicates the type or category of an instruction set associated with a processor or computing architecture.
-
B.
numberOfGeneralPurposeRegisters
Indicates the quantity of general-purpose registers associated with or available in a given computing context.
-
C.
cpuArchitecture
Indicates the type of processor instruction set or hardware architecture that a computing system or component is designed to run on.
-
D.
bitWidth
Indicates the number of bits used to represent or encode a given value, type, or data element.
-
E.
coreCountCPU
Indicates the number of processing cores that a CPU has.
- F. None of above. chosen
Provenance (4 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69a498dba1d8819093b46a3a8d2485f1 |
completed | March 1, 2026, 7:51 p.m. |
| NER | Named-entity recognition | batch_69a4c6f0ce988190aafab4a6e0dfd710 |
completed | March 1, 2026, 11:08 p.m. |
| PD | Predicate disambiguation | batch_69a4c48a8cf48190a6ebf8d44a608a06 |
completed | March 1, 2026, 10:58 p.m. |
| PDg | Predicate description generation | batch_69a4c4feea448190b2b5071b28a5b608 |
completed | March 1, 2026, 11 p.m. |
Created at: March 1, 2026, 8:12 p.m.