Triple

T13764595
Position Surface form Disambiguated ID Type / Status
Subject Motorola 68060 E330704 entity
Predicate supports P516 FINISHED
Object IEEE 754 floating-point (with FPU enabled variants) E1460 NE FINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: IEEE 754 floating-point (with FPU enabled variants) | Statement: [Motorola 68060, supports, IEEE 754 floating-point (with FPU enabled variants)]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07 
Target entity: IEEE 754 floating-point (with FPU enabled variants)
Context triple: [Motorola 68060, supports, IEEE 754 floating-point (with FPU enabled variants)]
  • A. IEEE 754 floating‑point arithmetic standard chosen
    The IEEE 754 floating‑point arithmetic standard is the globally adopted specification that defines formats and rules for representing and performing binary and decimal floating‑point calculations in computer systems.
  • B. VFP floating-point extension
    The VFP floating-point extension is an ARM architecture coprocessor feature that provides hardware support for high-performance single- and double-precision floating-point arithmetic.
  • C. x87 FPU
    The x87 FPU is the dedicated floating-point coprocessor architecture used in IA-32 processors to perform hardware-accelerated arithmetic on real and complex numbers.
  • D. CP1 floating-point coprocessor
    The CP1 floating-point coprocessor is a dedicated hardware unit used in MIPS architectures to perform floating-point arithmetic operations efficiently.
  • E. V (vector extension)
    V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
  • F. None of above.
  • G. Unsure - the case is ambiguous/there is not enough information to decide.

Provenance (3 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69d81c583b0081909e408a17db517a21 completed April 9, 2026, 9:38 p.m.
NER Named-entity recognition batch_69de022690ac8190bd5410ecc659a2a7 completed April 14, 2026, 9 a.m.
NED1 Entity disambiguation (via context triple) batch_69f7a862e6808190b8fbb27304212058 completed May 3, 2026, 7:56 p.m.
Created at: April 9, 2026, 10:10 p.m.