Statements (23)
| Predicate | Object |
|---|---|
| gptkbp:instanceOf |
gptkb:microprocessor
|
| gptkbp:announced |
2017
|
| gptkbp:architecture |
gptkb:RISC-V
|
| gptkbp:cache |
configurable
|
| gptkbp:heldBy |
RV32IMAC
|
| gptkbp:intendedUse |
embedded applications
|
| gptkbp:manufacturer |
gptkb:SiFive
|
| gptkbp:openSource |
no
|
| gptkbp:pipeline_stages |
5
|
| gptkbp:supports |
gptkb:AMBA_AXI4_interface
gptkb:JTAG_debug hardware multiply/divide interrupts atomic instructions single-issue |
| gptkbp:targetMarket |
gptkb:IoT
microcontrollers |
| gptkbp:type |
in-order
|
| gptkbp:used_in |
gptkb:SiFive_Freedom_E300_platform
|
| gptkbp:width |
32-bit
|
| gptkbp:bfsParent |
gptkb:HiFive1
|
| gptkbp:bfsLayer |
7
|
| https://www.w3.org/2000/01/rdf-schema#label |
SiFive E31 RISC-V Core
|