NDS32
E986964
UNEXPLORED
NDS32 is a 32-bit RISC processor architecture developed by Andes Technology, designed for embedded systems and supported by various open-source toolchains.
All labels observed (1)
| Label | Occurrences |
|---|---|
| NDS32 canonical | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T12514711 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: NDS32 Context triple: [GNU As, supportsTarget, NDS32]
-
A.
Nios II
Nios II is a soft-core 32-bit RISC processor architecture developed by Altera (now Intel) for implementation on FPGA devices.
-
B.
RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
-
C.
MIPS
MIPS is an infrared imaging and photometry instrument that operated aboard the Spitzer Space Telescope, used to study celestial objects at multiple mid- to far-infrared wavelengths.
-
D.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
E.
Tensilica Xtensa LX6
Tensilica Xtensa LX6 is a customizable 32-bit RISC processor core widely used in embedded systems for its efficient performance and low power consumption, notably in Espressif’s ESP32 SoCs.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: NDS32 Target entity description: NDS32 is a 32-bit RISC processor architecture developed by Andes Technology, designed for embedded systems and supported by various open-source toolchains.
-
A.
Nios II
Nios II is a soft-core 32-bit RISC processor architecture developed by Altera (now Intel) for implementation on FPGA devices.
-
B.
RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
-
C.
MIPS
MIPS is an infrared imaging and photometry instrument that operated aboard the Spitzer Space Telescope, used to study celestial objects at multiple mid- to far-infrared wavelengths.
-
D.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
E.
Tensilica Xtensa LX6
Tensilica Xtensa LX6 is a customizable 32-bit RISC processor core widely used in embedded systems for its efficient performance and low power consumption, notably in Espressif’s ESP32 SoCs.
- F. None of above. chosen
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.