SH-1

E724208

SH-1 is the first-generation implementation of the SuperH 32-bit RISC microprocessor architecture developed for embedded systems.

All labels observed (1)

Label Occurrences
SH-1 canonical 3

How this entity was disambiguated

Statements (39)

Predicate Object
instanceOf microprocessor
addressSpace 32-bit
architectureGeneration first-generation SuperH
architectureType RISC
linked to: RISC architecture
belongsToArchitectureLine SuperH 32-bit RISC family
bitWidth 32-bit
codeCompatibility binary compatible within SuperH family (with constraints)
CPUArchitectureFamily SuperH
designedBy Hitachi
designedFor embedded systems
designGoal high performance per clock for embedded tasks
reduced instruction set complexity
endianSupport little-endian
hasFeature compact 16-bit instruction encoding for 32-bit core
on-chip peripheral integration (in SoC implementations)
instructionSetArchitecture SuperH ISA
linked to: SuperH
laterAssociatedWith Renesas Technology
linked to: Renesas Electronics
marketSegment embedded microcontrollers
embedded microprocessors
optimizedFor code density
low cost
low power consumption
pipelineType simple RISC pipeline
registerCountType 32-bit general-purpose registers
registerFileType general-purpose registers
successor SH-2
supports conditional branch instructions
integer arithmetic operations
load-store architecture
logical operations
shift and rotate operations
technologyDomain embedded computing
microcontroller-based systems
typicalUseCase automotive control units
consumer electronics
embedded controllers
industrial embedded systems
usesInstructionEncoding fixed-length 16-bit instructions
wordLength 32-bit

How these facts were elicited

Referenced by (3)

Full triples — surface form annotated when it differs from this entity's canonical label.