Intel Haswell microarchitecture
E640802
The Intel Haswell microarchitecture is a generation of Intel CPU design that introduced significant performance and efficiency improvements over its predecessors, including enhanced vector processing, integrated graphics, and power management features.
All labels observed (1)
| Label | Occurrences |
|---|---|
| Intel Haswell microarchitecture canonical | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T7086808 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
Target entity: Intel Haswell microarchitecture Context triple: [Intel AVX2, firstSupportedBy, Intel Haswell microarchitecture]
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A.
Tiger Lake microarchitecture
Tiger Lake microarchitecture is Intel’s 11th-generation Core CPU design for laptops, featuring improved performance, power efficiency, and integrated Iris Xe graphics on a 10 nm SuperFin process.
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B.
Broadwell
Broadwell is a small rural village in Oxfordshire, England, known for its traditional Cotswold stone buildings and historic parish church.
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C.
Apollo Lake platform
The Apollo Lake platform is Intel’s low-power system-on-chip family for entry-level PCs and embedded devices, built around the Goldmont CPU microarchitecture.
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D.
Intel Atom
Intel Atom is a line of low-power x86 microprocessors designed primarily for energy-efficient laptops, netbooks, and embedded devices.
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E.
Intel 64
Intel 64 is Intel’s 64-bit architecture extension that enables x86 processors to handle 64-bit computing, including larger memory addressing and enhanced performance for modern applications.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Target entity: Intel Haswell microarchitecture Target entity description: The Intel Haswell microarchitecture is a generation of Intel CPU design that introduced significant performance and efficiency improvements over its predecessors, including enhanced vector processing, integrated graphics, and power management features.
-
A.
Tiger Lake microarchitecture
Tiger Lake microarchitecture is Intel’s 11th-generation Core CPU design for laptops, featuring improved performance, power efficiency, and integrated Iris Xe graphics on a 10 nm SuperFin process.
-
B.
Broadwell
Broadwell is a small rural village in Oxfordshire, England, known for its traditional Cotswold stone buildings and historic parish church.
-
C.
Apollo Lake platform
The Apollo Lake platform is Intel’s low-power system-on-chip family for entry-level PCs and embedded devices, built around the Goldmont CPU microarchitecture.
-
D.
Intel Atom
Intel Atom is a line of low-power x86 microprocessors designed primarily for energy-efficient laptops, netbooks, and embedded devices.
-
E.
Intel 64
Intel 64 is Intel’s 64-bit architecture extension that enables x86 processors to handle 64-bit computing, including larger memory addressing and enhanced performance for modern applications.
- F. None of above. chosen
Statements (51)
| Predicate | Object |
|---|---|
| instanceOf | CPU microarchitecture ⓘ |
| architectureFamily | Intel Core NERFINISHED ⓘ |
| codename | Haswell NERFINISHED ⓘ |
| coreCountRange | 2 to 18 cores ⓘ |
| designGoal |
better power efficiency for mobile devices
ⓘ
enhanced integrated graphics performance ⓘ improved performance per watt ⓘ |
| developer | Intel NERFINISHED ⓘ |
| followedBy | Intel Broadwell microarchitecture ⓘ |
| graphicsArchitecture | Intel HD Graphics 4000 series successor ⓘ |
| graphicsBranding | Intel HD Graphics NERFINISHED ⓘ |
| graphicsBranding |
Intel Iris Graphics
NERFINISHED
ⓘ
Intel Iris Pro Graphics NERFINISHED ⓘ |
| instructionSetArchitecture | x86-64 NERFINISHED ⓘ |
| launchYear | 2013 ⓘ |
| marketSegment |
desktop
ⓘ
mobile ⓘ server ⓘ workstation ⓘ |
| notableChangeFromPredecessor |
improved branch prediction and execution engine
ⓘ
integrated voltage regulator on-die ⓘ introduction of AVX2 vector instructions ⓘ |
| precededBy | Intel Ivy Bridge microarchitecture NERFINISHED ⓘ |
| processNode | 22 nm ⓘ |
| processTechnology | 22 nm tri-gate ⓘ |
| socket |
LGA 1150
ⓘ
LGA 2011-v3 NERFINISHED ⓘ |
| supportsFeature |
Hyper-Threading
NERFINISHED
ⓘ
Turbo Boost 2.0 NERFINISHED ⓘ deep C-states ⓘ enhanced power management ⓘ improved branch prediction ⓘ improved out-of-order execution ⓘ integrated graphics ⓘ integrated voltage regulator ⓘ package C7 state ⓘ |
| supportsInstructionSet |
x86
NERFINISHED
ⓘ
x86-64 ⓘ |
| supportsInstructionSetExtension |
AES-NI
ⓘ
AVX ⓘ AVX2 NERFINISHED ⓘ BMI1 ⓘ BMI2 NERFINISHED ⓘ FMA3 ⓘ SSE4.1 NERFINISHED ⓘ SSE4.2 NERFINISHED ⓘ TSX NERFINISHED ⓘ |
| supportsMemoryChannelCount |
dual-channel
ⓘ
quad-channel ⓘ |
| supportsMemoryType |
DDR3
ⓘ
DDR3L NERFINISHED ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Subject: Intel Haswell microarchitecture Description of subject: The Intel Haswell microarchitecture is a generation of Intel CPU design that introduced significant performance and efficiency improvements over its predecessors, including enhanced vector processing, integrated graphics, and power management features.
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.