P6
E637110
P6 is Intel’s sixth-generation x86 microarchitecture that introduced out-of-order and speculative execution, forming the basis for later Pentium II/III and early Core designs.
All labels observed (1)
| Label | Occurrences |
|---|---|
| P6 canonical | 2 |
How this entity was disambiguated
This entity first appeared as the object of triple T7032999 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: P6 Context triple: [Intel Pentium Pro, microarchitecture, P6]
-
A.
P5
P5 is the CERN Large Hadron Collider interaction point that hosts the CMS experiment and associated infrastructure.
-
B.
P5
P5 is a common abbreviation for the “Power Five,” the group of the five most prominent NCAA Division I college athletic conferences in the United States.
-
C.
P.
P. is a common abbreviated form of the Roman praenomen "Publius," frequently used in historical and classical texts.
-
D.
P
P is the vehicle registration code used on license plates for the Lithuanian city of Panevėžys.
-
E.
P
P is the vehicle registration code used on license plates for the Czech city of Plzeň.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: P6 Target entity description: P6 is Intel’s sixth-generation x86 microarchitecture that introduced out-of-order and speculative execution, forming the basis for later Pentium II/III and early Core designs.
-
A.
P5
P5 is the CERN Large Hadron Collider interaction point that hosts the CMS experiment and associated infrastructure.
-
B.
P5
P5 is a common abbreviation for the “Power Five,” the group of the five most prominent NCAA Division I college athletic conferences in the United States.
-
C.
P.
P. is a common abbreviated form of the Roman praenomen "Publius," frequently used in historical and classical texts.
-
D.
P
P is the vehicle registration code used on license plates for the Lithuanian city of Panevėžys.
-
E.
P
P is the vehicle registration code used on license plates for the Czech city of Plzeň.
- F. None of above. chosen
Statements (48)
| Predicate | Object |
|---|---|
| instanceOf |
Intel x86 microarchitecture
ⓘ
microarchitecture ⓘ |
| architectureFamily | x86 ⓘ |
| basisFor |
Pentium II
ⓘ
linked to:
Intel Pentium II
Pentium II Xeon ⓘ
linked to:
Intel Pentium II
Pentium III ⓘ
linked to:
Intel Pentium III
Pentium III Xeon ⓘ
linked to:
Intel Pentium III
Pentium Pro ⓘ
linked to:
Intel Pentium Pro
early Intel Core microarchitecture designs ⓘ |
| branchPrediction | dynamic branch predictor ⓘ |
| compatibility | IA-32 ⓘ |
| designer |
Intel
ⓘ
linked to:
Intel Corporation
|
| designGoal |
higher performance per clock
ⓘ
improved efficiency over P5 ⓘ |
| executionModel |
out-of-order
ⓘ
speculative ⓘ |
| familyName |
P6 microarchitecture family
ⓘ
linked to:
P6 microarchitecture
|
| generation | sixth-generation x86 ⓘ |
| influenced |
Intel Core microarchitecture
ⓘ
later x86 microarchitectures ⓘ |
| introducedFeature |
dynamic branch prediction
ⓘ
micro-ops based execution ⓘ non-blocking caches ⓘ out-of-order execution ⓘ register renaming ⓘ reorder buffer ⓘ reservation stations ⓘ speculative execution ⓘ speculative retirement of instructions ⓘ super-scalar execution ⓘ superpipelined design ⓘ |
| marketSegment |
desktop computers
ⓘ
server computers ⓘ workstation computers ⓘ |
| notableCPUCore | P6 core ⓘ |
| notableImprovementOverPredecessor |
better branch prediction
ⓘ
higher instructions per cycle ⓘ improved floating-point performance ⓘ |
| pipelineType | superpipelined ⓘ |
| successorTo |
Intel P5 microarchitecture
ⓘ
linked to:
P6 microarchitecture
P5 ⓘ |
| usedIn |
Pentium II Xeon processors
ⓘ
linked to:
Intel Pentium II
Pentium II processors ⓘ
linked to:
Intel Pentium II
Pentium III Xeon processors ⓘ
linked to:
Intel Pentium III
Pentium III processors ⓘ
linked to:
Intel Pentium III
Pentium Pro processors ⓘ
linked to:
Intel Pentium Pro
|
| vendor |
Intel
ⓘ
linked to:
Intel Corporation
|
| wordSize | 32-bit ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: P6 Description of subject: P6 is Intel’s sixth-generation x86 microarchitecture that introduced out-of-order and speculative execution, forming the basis for later Pentium II/III and early Core designs.
Referenced by (2)
Full triples — surface form annotated when it differs from this entity's canonical label.